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Mechanistic Analysis of the Effect of Gap on Convex Curves of Wafer in Double-Sided Polishing  ( SCI-EXPANDED收录 EI收录)  

文献类型:期刊文献

英文题名:Mechanistic Analysis of the Effect of Gap on Convex Curves of Wafer in Double-Sided Polishing

作者:Chen, Jiayu[1,2];Liu, Yiran[3];Wang, Xiangang[4];Cao, Jun[4];Yu, Wenjie[5];Zhu, Lei[5]

机构:[1]Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, State Key Lab Mat Integrated Circuits, Shanghai 200050, Peoples R China;[2]Univ Shanghai Sci andTechnol, Sch Mat & Chem, Shanghai 200093, Peoples R China;[3]Fudan Univ, Sch Microelect, State Key Lab Integrated Chips & Syst, Shanghai 200433, Peoples R China;[4]East China Univ Sci & Technol, Sch Mech & Power Engn, Shanghai 200237, Peoples R China;[5]Chinese Acad Sci, Shanghai Inst Microsyst & Informat Technol, Shanghai 200050, Peoples R China

年份:2025

卷号:38

期号:3

起止页码:571

外文期刊名:IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING

收录:;EI(收录号:20252218527946);WOS:【SCI-EXPANDED(收录号:WOS:001563976700002)】;

语种:英文

外文关键词:Trajectory; Stress; Semiconductor device modeling; Silicon; Kinematics; Gears; Surface treatment; Mathematical models; Finite element analysis; Motion segmentation; Contact stress; convex-concave curves; double-sided polishing; gap; relative path

摘要:Double-Sided Polishing (DSP) is a critical process for achieving flatness in silicon wafers. This study explores the relationship between the variations in the gap between polishing plates and the surface convexity of wafers. The study indicates that differences in the gap between the upper and lower plates affect the stress distribution on the wafers, altering the removal rate at different positions during the DSP process. This results in the formation of convex curves on the wafer surface. Additionally, this research proposes a calculation method to determine the convex curves, by coupling the contact stress on wafer surface with its relative motion path to the pad, to calculate the removal amount at different positions. The reliability of the model was ultimately verified through experimental results. This method provides guidance for optimizing DSP processes to improve wafer flatness.

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