文献类型：期刊文献

英文题名：Using module-level evolvable hardware approach in design of sequential logic circuits

作者：Tao, Yanyun[1,2]; Cao, Jian[1]; Zhang, Yuzhen[3]; Lin, Jiajun[4]; Li, Minglu[1]

机构：[1] Computer Science, Shanghai Jiao Tong University, Shanghai, 200240, China; [2] School of Urban Rail Transportation, Soochow University, Suzhou, 215005, China; [3] Soochow University, Suzhou, 215006, China; [4] Institute of Automation, East China University of Science and Technology, Shanghai, 200237, China

年份：2012

外文期刊名：2012 IEEE Congress on Evolutionary Computation, CEC 2012

收录：EI(收录号：20124015500629)

语种：英文

外文关键词：Genetic algorithms - Sequential circuits - Computer circuits - Timing circuits - Electric network analysis

摘要：In this study, we propose a module-level Evolvable Hardware (EHW) approach to design synchronous sequential circuits and minimize the circuit complexity (the number of logic gates and wires used). Firstly, we use Genetic Algorithm (GA) to implement state simplification and obtain near-optimal state assignment. Then, in the pre-evolution stage, EHW evolves a set of high performing circuits and uses data mining method to find frequently evolved blocks from these circuits. The frequently evolved block would be re-used as function or terminal for evolving better circuits in the re-evolution stage. EHW has a faster convergence so that the circuit with small complexity could be evolved. Auto starting ability of circuits would also be test by the fitness function of EHW. Finally, sequence detectors, modulon counters, and ISCAS'89 circuit are used as the proof for our evolutionary design approach. Simulation results are given, and our evolutionary algorithm is shown to be better than other methods in terms of convergence time, success rate, and maximum fitness across generations. ? 2012 IEEE.