文献类型：期刊文献

英文题名：Interconnection Allocation Between Functional Units and Registers in High-Level Synthesis

作者：Hao, Cong[1];Ni, Jianmo[2];Wang, Nan[3];Yoshimura, Takeshi[1]

机构：[1]Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka 8080135, Japan;[2]Shanghai Jiao Tong Univ, Sch, Shanghai 200240, Peoples R China;[3]East China Univ Sci & Technol, Sch Informat Sci & Engn, Shanghai 200237, Peoples R China

年份：2017

卷号：25

期号：3

起止页码：1140

外文期刊名：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

收录：;EI(收录号：20173404062936);WOS:【SCI-EXPANDED(收录号:WOS:000395894000030)】；

基金：This work was supported by KAKENHI under Grant 26420323.

语种：英文

外文关键词：Graphical methodology; high-level synthesis (HLS); interconnection; simplex method

摘要：Data path interconnection on VLSI chips usually consumes a significant amount of both power and area. In this paper, we focus on the port assignment problem for binary commutative operators for interconnection complexity reduction. First, the port assignment problem is formulated on a constraint graph, and a practical method is proposed to find a valid and initial solution. For solution optimization, an elementary spanning-tree-transformation-based local search algorithm is proposed. To improve the efficiency of optimization, a matrix formulation, which meets the simplex tabuleau format, is proposed and thus the simplex method is adopted for optimization. Moreover, operation pivoting and successive pivoting are discussed for algorithm speedup. The experimental results show that on the randomly generated test cases, the matrix-based algorithm shows the highest solution optimality and is five times faster than the elementary transformation method. On the real high-level synthesis benchmarks, the matrix-based method reduced 14% interconnections, while the previous greedy algorithm reduced 8% on average.