文献类型：期刊文献

中文题名：三相数字锁相环的原理及性能

英文题名：Principle and Performance of the Three-Phase Digital Phase-Locked Loop

作者：龚锦霞[1];解大[1];张延迟[2,3]

机构：[1]上海交通大学电子信息与电气工程学院,上海200240;[2]华东理工大学自动化系,上海200237;[3]上海电机学院电气工程系,上海200240

年份：2009

卷号：24

期号：10

起止页码：94

中文期刊名：电工技术学报

外文期刊名：Transactions of China Electrotechnical Society

收录：CSTPCD;;EI(收录号：20094912530362);Scopus;北大核心:【北大核心2008】；CSCD:【CSCD2011_2012】；

语种：中文

中文关键词：三相锁相环;偏移;不对称;谐波;变频;仿真

外文关键词：Three-phase phase-locked loop （PLL）, offsetting, unbalance, harmonic, variable frequency, simulation

摘要：分析了三相锁相环的基本原理、特性及各种输入情况下锁相环的输出性能。通过理论推导,在三相输入信号存在直流偏移、不对称、谐波等干扰情况下,分析了三相锁相环的检测相位误差,得出谐波的含量。并通过仿真研究,验证了三相输入信号存在直流偏移、不对称、谐波等干扰情况下,仿真结果与理论推导一致。并对相位突变和频率突变的情况进行了仿真研究,说明在相位和频率发生变动时三相锁相环仍能有效地锁定相位,能够满足系统变频的要求。
This paper analyzes the fundamental principle and performance of three-phase phase-locked loop. and the harmonic component in variable situations. It deducts the error influence on three-phase locked phase when the three-phase input signals are offsetting, unbalanced or with harmonics. The theoretical conclusions are confirmed by detailed simulations under the situations, such as offsetting, unbalance, harmonic, phase-abrupt and frequency-abrupt. The simulation results prove that the three-phase phase-locked loop can work well in disturbance situation and variable frequency system when the frequency of the inputs is variable.