文献类型：期刊文献

中文题名：高速并行总线信号完整性分析设计

英文题名：Signal integrity analysis in parallel bus designing

作者：倪芸[1];姚晓东[1]

机构：[1]华东理工大学信息科学与工程学院,上海200237

年份：2013

卷号：36

期号：4

起止页码：106

中文期刊名：电子测量技术

外文期刊名：Electronic Measurement Technology

收录：CSTPCD

语种：中文

中文关键词：信号完整性;并行总线;Cadence;Allegro;信号反射

外文关键词：signal integrity; parallel; Cadence Allegro; signal reflection

摘要：在集成电路的设计中,常常会遇到CPU与SDRAM或者CPU与Flash之间的高速并行数据总线、地址总线接口设计,为了解决信号完整性问题,可以利用Cadence Allegro软件中的SigXplorer工具,加载入芯片厂商的元器件IBIS模型后,对高速并行总线进行信号特性的仿真观测和分析,继而为电路设计提供依据。设计时运用多种传输线终端匹配策略来抑制和消除信号线上的传输反射。仿真结果表明:合适的总线终端电阻端接方式有利于抑制传输线信号反射,利用仿真软件来选择合理的端接方案和元件参数,对总线以及信号完整性设计具有重要意义。
There usually exists the design of high-speed parallel data and address bus interface between CPU SDRAM and CPU＆Flash when design integrated circuits. In order to solve the problems of signal integrity, we can use the SigXplorer tools in Cadence Allegro. After load the IBIS model of the chip manufacturers＇instruments,observe and analyze the signal characteristics of high-speed parallel bus by simulating. The simulation can provide the basis for circuit design. In this paper, diverse conjunction strategies are connected to delivering line, in order to eliminate transmission reflection. The simulation results show that an appropriate conjunct resistance and conjunction method can restrain signal reflection. Using software simulation to select reasonable method and component value, which is significant in bus and signal integrity design.