详细信息

Synchronization Error Estimation and Controller Design for Delayed Lur'e Systems With Parameter Mismatches  ( SCI-EXPANDED收录 EI收录)  

文献类型:期刊文献

英文题名:Synchronization Error Estimation and Controller Design for Delayed Lur'e Systems With Parameter Mismatches

作者:He, Wangli[1,2];Qian, Feng[1];Han, Qing-Long[2,3];Cao, Jinde[4]

机构:[1]E China Univ Sci & Technol, Minist Educ, Key Lab Adv Control & Optimizat Chem Proc, Shanghai 200237, Peoples R China;[2]Cent Queensland Univ, Ctr Intelligent & Networked Syst, Rockhampton, Qld 4702, Australia;[3]Cent Queensland Univ, Sch Informat & Commun Technol, Rockhampton, Qld 4702, Australia;[4]Southeast Univ, Dept Math, Nanjing 210096, Jiangsu, Peoples R China

年份:2012

卷号:23

期号:10

起止页码:1551

外文期刊名:IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS

收录:;EI(收录号:20131916310224);WOS:【SCI-EXPANDED(收录号:WOS:000308966100004)】;

基金:This work was supported in part by the National 973 Project under Grant 2012CB720500, the Key Program of National Natural Science Foundation of China under Grant U1162202, the Fundamental Research Funds for the Central Universities, the Shanghai Leading Academic Discipline Project under Grant B504, the Australian Research Council Discovery Projects under Grant DP1096780 and Grant DP0986376, and the Research Advancement Awards Scheme Program (from 2010 to 2012) at Central Queensland University, Australia.

语种:英文

外文关键词:Delayed Lur'e systems; neural networks; parameter mismatches; synchronization

摘要:This paper investigates the problem of master-slave synchronization of two delayed Lur'e systems in the presence of parameter mismatches. First, by analyzing the corresponding synchronization error system, synchronization with an error level, which is referred to as quasi-synchronization, is established. Some delay-dependent quasi-synchronization criteria are derived. An estimation of the synchronization error bound is given, and an explicit expression of error levels is obtained. Second, sufficient conditions on the existence of feedback controllers under a predetermined error level are provided. The controller gains are obtained by solving a set of linear matrix inequalities. Finally, a delayed Chua's circuit is chosen to illustrate the effectiveness of the derived results.

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