文献类型：期刊文献

英文题名：Power-gating-aware scheduling with effective hardware resources optimization

作者：Wang, Nan[1];Zhong, Wei[2];Chen, Song[2];Ma, Zhiyuan[3];Ling, Xiaofeng[1];Zhu, Yu[1]

机构：[1]East China Univ Sci & Technol, Sch Informat Sci & Engn, Shanghai 200237, Peoples R China;[2]Univ Sci & Technol China, Dept Elect Sci & Technol, Hefei 230027, Anhui, Peoples R China;[3]Univ Elect Sci & Technol China, Sch Comp Sci & Engn, Chengdu, Sichuan, Peoples R China

年份：2018

卷号：61

起止页码：167

外文期刊名：INTEGRATION-THE VLSI JOURNAL

收录：;EI(收录号：20180104598942);WOS:【SCI-EXPANDED(收录号:WOS:000428822600016)】；

基金：This work was supported by the National Natural Science Foundation of China (NSFC) under Grant 61604054. The work of W. Zhong and S. Chen was supported by the NSFC under Grant 61732020.

语种：英文

外文关键词：Scheduling; Power-gating; Retention register; Hardware resources optimization

摘要：Power-gating technology has been widely used to reduce subthreshold leakage power. However, the efficiency of power-gating degrades significantly with the wide use of retention registers. The scheduling algorithms proposed in this work optimize the number of required retention registers to minimize the leakage power when the supply voltage of data-path is cut off; in addition, the hardware resources, including functional units, registers and interconnections, undergo overall optimization to enhance the quality of the scheduling results. For each possible scheduling result of an operation, the life times of related values are analyzed together to provide a tight lower bound of active values in each control step, the maximum of which equals the number of required registers. A max-cost flow-based algorithm is also implemented on a network derived from the current mobilities, and the total cost over this network evaluates the interconnection benefits of the current schedule. With an overall analysis of hardware resource usages, the operation scheduling order is finally determined by iteratively executing a maximum weight independent set-based method. The experimental results show the proposed algorithms optimize both the leakage power and the area of the circuit by effectively reducing the hardware resource usages.