文献类型：期刊文献

英文题名：Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design

作者：Wang, Nan[1];Zhong, Wei[2];Hao, Cong[3];Chen, Song[2];Yoshimura, Takeshi[3];Zhu, Yu[1]

机构：[1]East China Univ Sci & Technol, Sch Informat Sci & Engn, Shanghai 200237, Peoples R China;[2]Univ Sci & Technol China, Sch Informat Sci & Technol, Hefei 230026, Peoples R China;[3]Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka 8080135, Japan

年份：2016

卷号：24

期号：10

起止页码：3067

外文期刊名：IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

收录：;EI(收录号：20161202133499);WOS:【SCI-EXPANDED(收录号:WOS:000385407700005)】；

基金：This work was supported by the National Natural Science Foundation of China under Grant 61271349 and Grant 61501187. The work of W. Zhong and S. Chen was supported by the National Natural Science Foundation of China under Grant 61404123.

语种：英文

外文关键词：Dual-V-th; functional unit; leakage-power optimization; scheduling

摘要：The exponential increase in leakage power and the substantial power-saving opportunities provided by scheduling have made dual-threshold voltage (dual-V-th) an attractive choice for low-leakage-power designs. In this paper, we work under the assumption that functional units (FUs) are allocated after scheduling, and fully explore the solution space of scheduling with dual-V-th operations to optimize the leakage power of the FUs. First, a binding conflict graph (BCG)-based scheduling method is presented to minimize the number of FUs. Second, the BCG-based method is extended to allow scheduling with dual-V-th operation targeting the minimization of leakage power. In timing-constrained scheduling, each operation in the data flow is initialized with low-V-th. Then, starting from an operation schedule with the timing constraint satisfied, we scale the sets of low-V-th operations in the off-critical paths with high-V-th so as to reduce the number of low-V-th FUs without increasing the total delay. Finally, a scheduling method for minimizing the leakage power under both timing and resource constraints is presented. The results of benchmark tests show that the proposed algorithms can reduce the leakage power reported in previous works by 10.2% while maintaining high circuit performance.